Initially, when power is applied to a full or half H-bridge circuit, before the digital logic settles to the correct state, both the high and low sides on a half H-bridge side can be ON at the same time. The chip can blow up because of excessive currents during this shoot-through event.
For integrated circuit chips that contain a Full or half H-bridge circuit, the digital power supply rails take time to settle during power up. During that time interval, which can be on the order of a few micro seconds, if the digital control signals to the high side and low side drive level shifters are not correct, both the high and low side FET's can both be ON at the same time. The chip can blow up because of excessive currents during this shoot-through event.
A typical prior art half H-bridge circuit is shown in FIG. 1. Transistor M0 is called the high side FET and its drain is connected to the main power supply Vdd. The gate of high side FET M0 is driven by high side level shifter 20 which is usually supplied by charge pump voltage. Transistor M1 is called a Low side FET and its source is connected to Ground. The gate of low side FET M1 is driven by low side level shifter 22. In normal operation, both the high and low sides are never ON at the same time.
Both the high and low side digital control signal inputs to the level shifters 20 and 22 are from a digital logic core 24. During power up, if the digital logic power supply (3.3 V—Digital Rail shown in FIG. 1) takes time to settle to its final value, the control signals could be in the wrong state instructing the level shifters 20 and 22 to turn ON both the high and low side FET's M0 and M1 at the same time. During this event called shoot-through, excessive currents flow between the main power supply Vdd and ground through the high and low side FET's M0 and M1. The chip potentially can blow up during shoot-through.
Two prior art architectures are shown in FIGS. 1 & 2. On the first architecture, shown in FIG. 1, there is no attempt to control the shoot through event. On the second architecture, shown in FIG. 2, there are passive devices (resistors) R1 and R2 placed from the gate node to ground. This potentially decreases shoot-through, but during normal operation when the FET's M0 and M1 are supposed to be ON, there is a leakage current to ground. On the high side, since the gate is driven by a chargepump voltage, the chargepump is unnecessarily strained.